With the number of transistors in modern Very Large Scale Integrated (VLSI) circuit designs continuing to increase, the task of finding problems within the mask layout shapes can be difficult. One such problem that often occurs is when a design is run through a Layout vs. Schematic (LVS) tool that requires certain intermediate mask levels to be in the same level of hierarchy. Due to hierarchical interactions, such intermediate mask levels that are the result of Boolean operations within the runset may end up at a level different in the hierarchy than one of the original mask levels, and subsequent Boolean operations on these levels may fail due to this change in hierarchy. Finding such shapes or polygons in a mask layout tool can often be difficult due to the shear size of the layout, the number of levels of hierarchy, and the number of intermediate mask levels produced by the tool runset.
The current method of debugging such problems involves opening up the mask layout, querying individual shapes, reading the hierarchical description that the shapes reside in using a status window, and comparing the text of various shapes. Such a query may result in a description such as this:                “Rectangle on CA at (16.936,158.414) nested on internal view “lib_A cell_A layout”. Placement: [mir=false,rot=0,x=17.328,y=25.289] Hierarchy: view(lib_A cell_A layout) trans/view(lib_A cell_B layout) trans/view(lib_A cell_C layout) trans/view(lib_A cell_D layout) trans/view(lib_A cell_E layout) trans/view(lib_B cell_F layout) comp(I2)/view(lib_B cell_G layout) comp(I18)/view(lib_B cell_H layout) comp(I1)/view(lib_B cell_I layout) comp(I1)/view(lib_B cell_J layout) trans/view(lib_B cell_K layout) trans/view(lib_B cell_L layout)”        
An alternate method involves turning on only certain levels of hierarchy at a time, then flipping between the hierarchical levels to make comparisons. However, both of these methods are time consuming, error prone, and cumbersome.